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137
9151AINDCO07/09
ATA8742
tem clock frequency (f
ExtClk
 < f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 22-2.  Prescaler for Timer/Counter0
Note:
1.  The synchronization logic on the input pins (T0) is shown in Figure 22-1 on page 136.
22.1   Register Description
22.1.1
GTCCR  General Timer/Counter Control Register
"  Bit 7  TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by
hardware, and the Timer/Counter start counting.
"  Bit 0  PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
PSR10
Clear
clk
T0
T0
clk
I/O
Synchronization
Bit
7
6
5
4
3
2
1
0
0x23 (0x43)
TSM






PSR10
GTCCR
Read/Write
R/W
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
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